External Modules

An external module is a module that is defined in the host language but made accessible to Virdant.

External modules are declared using the ext modifier before the mod keyword:

ext mod Memory {
    incoming addr : Word[16];
    outgoing data : Word[8];
}

An external module may only declare ports.

The Virdant compiler will create a stub to read code written in the host language. Today, this will look up a Verilog file in a special directory whose name matches the module definition:

Memory.v
 1module Memory(
 2  input  wire [15:0] addr,
 3  output reg  [7:0]  data
 4);
 5    reg [7:0] mem[1 << 16];
 6
 7    always @(*) begin
 8        data = mem[addr];
 9    end
10
11    initial begin
12        $readmemh("memory.hex", mem);
13    end
14endmodule

External modules are useful for gaining access to features the host language provides but Virdant does not. For example, you can use them to call system tasks, like $display, add SystemVerilog assertions to your design, define behavioral memories, define clock generators, or instantiate a module your synthesis tool provides.